Although bipolar transistors were available before MOS transistors, in recent years the emphasis has been on MOS transistors, particularly complementary MOS (CMOS) transistors. However, bipolar transistors do have some advantages over MOS transistors, including higher transconductance, higher output impedance and faster switching speed, and, in vertical form, the ability generally to sink larger currents per unit device area.
For this reason, there are circuit applications where it is desirable to include both bipolar transistors and MOS transistors, particularly CMOS transistors. Moreover, because of the advantages of monolithic integrated circuits, it is desirable in such circuit applications to incorporate both forms of transistors in a common semiconductive substrate or individual chip.
Among the circuit applications where such a monolithic integrated circuit is expected to be useful are linear circuits, such as temperature stable voltage regulators, bandgap reference circuits, low input offset circuits, and feedback amplifier circuits.
Moreover, for ease of manufacture, it is desirable to have a fabrication process in which both bipolar and MOS transistors are essentially formed in parallel with a minimum of processing steps.
These factors have been recognized in a paper entitled, "An Isolated Vertical n-p-n Transistor in an n-Well CMOS Process", published in IEEE Journal of Solid State Circuits Vol. SC-20, No. 2, Apri1 1985, pages 489-493. In the process described therein, a vertical n-p-n transistor is formed in a chip along with low voltage CMOS transistors by modification of a standard process to change both the dosage of the implant used to form the source and drain of the PMOS transistor and the implant anneal conditions.